ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
When the Multiprocessing Extensions are not implemented, the format of the TTBR0 register is:
31 14-N 13-N 6 5 4 3 2 1 0
Translation table base 0 address UNK/SBZP RGN S
When the Multiprocessing Extensions are implemented, the format of the TTBR0 register is:
Bits [31:14-N] Translation table base 0 address, bits [31:14-N].
The value of N determines the required alignment of the translation table, which must be
aligned to 214-N bytes.
Bits [13-N:6], ARMv7-A base architecture
UNK/SBZP.
Bits [13-N:7], when the Multiprocessing Extensions are implemented
UNK/SBZP.
NOS IMP
31 14-N 13-N 7 6 5 4 3 2 1 0
Translation table base 0 address UNK/SBZP RGN S
IRGN[0]
NOS
IMP
IRGN[1]
IRGN[0], bit [6], when the Multiprocessing Extensions are implemented
See the description of bit [0] when the Multiprocessing Extensions are implemented.
NOS, bit [5] Not Outer Shareable bit. Indicates the Outer Shareable attribute for the memory associated
with a translation table walk that has the Shareable attribute, indicated by TTBR0.S == 1:
0 Outer Shareable
1 Inner Shareable.
This bit is ignored when TTBR0.S == 0.
This bit is only implemented from ARMv7.
RGN, bits [4:3]
Region bits. Indicates the Outer Cacheability attributes for the memory associated with the
translation table walks:
0b00 Normal memory, Outer Non-cacheable
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable
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