ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

eturn;
VCR_Recent_IRQ_NS_Valid = TRUE;
Debug Events
// VCRVectorMatch()
// ================
//
// The result of this function says whether iaddr and eaddr match for vector catch purposes:
// TRUE if they definitely match
// boolean UNKNOWN if it is UNPREDICTABLE whether they match
// FALSE if they definitely do not match
boolean VCRVectorMatch(bits(32) iaddr, boolean first, bits(32) eaddr)
match = FALSE;
unpred = FALSE;
if eaddr == iaddr then
if eaddr == iaddr then
// Exact address match is a definite match if on the first unit of the instruction,
// otherwise an UNPREDICTABLE match.
if first then match = TRUE; else unpred = TRUE;
else
// Check for other cases of UNPREDICTABLE matches.
case CurrentInstrSet() of
when InstrSet_ARM
unpred = TRUE;
when InstrSet_Thumb, InstrSet_ThumbEE
if iaddr == eaddr then unpred = TRUE;
if iaddr == ‘10’ && eaddr == ‘00’ then unpred = TRUE;
when InstrSet_Jazelle
if eaddr == ‘00’ then unpred = TRUE;
if eaddr == ‘10’ && iaddr == ‘11’ then unpred = TRUE;
if match then
return TRUE;
elsif unpred then
return boolean UNKNOWN;
else
return FALSE;
// VCRMatch()
// ==========
boolean VCRMatch(bits(32) address, boolean first)
// Determine addresses for IRQ and FIQ comparisons.
if SCTLR.VE == ‘0’ then
VCR_Recent_IRQ_S_Valid = FALSE; VCR_Recent_IRQ_NS_Valid = FALSE;
VCR_Recent_FIQ_S_Valid = FALSE; VCR_Recent_FIQ_NS_Valid = FALSE;
irq_addr = ExcVectorBase() + 24; irq_addr_v = TRUE;
fiq_addr = ExcVectorBase() + 28; fiq_addr_v = TRUE;
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C3-33