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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Virtual Memory System <strong>Architecture</strong> (VMSA)<br />

Four bits in the PRRR permit mapping of the Shareable attribute by defining, for the translation table<br />

S bit:<br />

— the meaning of S == 0 if the region is identified as Device memory<br />

— the meaning of S == 1 if the region is identified as Device memory<br />

— the meaning of S == 0 if the region is identified as Normal memory<br />

— the meaning of S == 1 if the region is identified as Normal memory.<br />

In each case, the meaning of the Shareable bit value is that the memory region is one of:<br />

— Shareable<br />

— Non-shareable.<br />

For each of the possible encodings of the TEX[0], C <strong>and</strong> B bits in a translation table entry, Table B3-9 shows<br />

which fields of the PRRR <strong>and</strong> NMRR registers describe the memory region attributes.<br />

To find the meaning of the value of the S bit in a translation table entry you must:<br />

use Table B3-9 to find the memory type of the region described by the entry<br />

if the memory type is Strongly-ordered then the region is Shareable<br />

Table B3-9 TEX, C, <strong>and</strong> B encodings when TRE == 1<br />

Encoding<br />

Memory typea Cache attributesa, b :<br />

TEX[0] C B Inner cache Outer cache<br />

Outer Shareable<br />

attribute b<br />

0 0 0 PRRR[1:0] NMRR[1:0] NMRR[17:16] NOT(PRRR[24])<br />

0 0 1 PRRR[3:2] NMRR[3:2] NMRR[19:18] NOT(PRRR[25])<br />

0 1 0 PRRR[5:4] NMRR[5:4] NMRR[21:20] NOT(PRRR[26])<br />

0 1 1 PRRR[7:6] NMRR[7:6] NMRR[23:22] NOT(PRRR[27])<br />

1 0 0 PRRR[9:8] NMRR[9:8] NMRR[25:24] NOT(PRRR[28])<br />

1 0 1 PRRR[11:10] NMRR[11:10] NMRR[27:26] NOT(PRRR[29])<br />

1 1 0 IMPLEMENTATION<br />

DEFINED<br />

IMPLEMENTATION<br />

DEFINED<br />

IMPLEMENTATION<br />

DEFINED<br />

IMPLEMENTATION<br />

DEFINED<br />

1 1 1 PRRR[15:14] NMRR[15:14] NMRR[31:30] NOT(PRRR[31])<br />

a. For details of the memory type field encodings see c10, Primary Region Remap Register (PRRR) on page B3-143. For<br />

details of the cache attribute encodings see Table B3-8 on page B3-34.<br />

b. Only applies if the memory type for the region is mapped as Normal memory <strong>and</strong> the location is Shareable.<br />

if the memory type is not Strongly-ordered then look up the memory type <strong>and</strong> value of the S bit in<br />

Table B3-10 on page B3-36 to find which bit of the PRRR defines the Shareable attribute of the<br />

region.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. B3-35

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