ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Where a change to the CP15 registers that is not yet guaranteed to be visible has an effect on exception
processing, the following rule applies:
When it is determined that an exception must be taken, any change of state held in CP15 registers
involved in the triggering of the exception and that affects the processing of the exception is
guaranteed to take effect before the exception is taken.
Therefore, in the following example, where initially A=1 and V=0, the LDR might or might not take a Data
Abort exception due to the unaligned access, but if an exception occurs the vector used is affected by the
Vbit:
MCR p15, R0, c1, c0, 0 ; clears the A bit and sets the V bit
LDR R2, [R3] ; unaligned load.
B3.12.5 Meaning of fixed bit values in register diagrams
In register diagrams, fixed bits are indicated by one of following:
0 In any implementation:
the bit must read as 0
writes to the bit must be ignored.
Software:
can rely on the bit reading as 0
must use an SBZP policy to write to the bit.
(0) In any implementation:
the bit must read as 0
writes to the bit must be ignored.
Software:
must not rely on the bit reading as 0
must use an SBZP policy to write to the bit.
1 In any implementation:
the bit must read as 1
writes to the bit must be ignored.
Software:
can rely on the bit reading as 1
must use an SBOP policy to write to the bit.
(1) In any implementation:
the bit must read as 1
writes to the bit must be ignored.
Software:
must not rely on the bit reading as 1
must use an SBOP policy to write to the bit.
Fields that are more than 1 bit wide are sometimes described as UNK/SBZP, instead of having each bit
marked as (0).
B3-78 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B