ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
On a read of DBGDSCRext, InstrCompl_l always returns the current value of InstrCompl.
The meanings of the values of InstrCompl_l are:
0 an instruction previously issued through the DBGITR has not completed its
changes to the architectural state of the processor
1 all instructions previously issued through the DBGITR have completed their
changes to the architectural state of the processor.
Normally, InstrCompl:
is cleared to 0 following issue of an instruction through DBGITR
becomes 1 once the instruction completes.
The taking of an exception marks the completion of the instruction. InstrCompl is set to 1 if
an instruction generates an Undefined Instruction or Data Abort exception.
InstrCompl is set to 1 on entry to Debug state. For more information about the behavior of
InstrCompl, InstrCompl_l and the DBGITR, see:
Instruction Transfer Register (DBGITR) on page C10-46
Host to Target Data Transfer Register (DBGDTRRX) on page C10-40
Target to Host Data Transfer Register (DBGDTRTX) on page C10-43.
Bits [27:24], v6 Debug and v6.1 Debug only
Reserved, UNK/SBZP.
ExtDCCmode, bits [21:20], v7 Debug only
The External DCC access mode field. This field controls the access mode for the external
views of the DCC registers and the Instruction Transfer Register (DBGITR). Possible values
are:
0b00 Non-blocking mode
0b01 Stall mode
0b10 Fast mode.
The values of 0b11 is reserved.
For details of the external DCC access modes see Access controls on the external view of the
DCC registers and DBGITR, v7 Debug only on page C10-21.
Bits [21:20], v6 Debug and v6.1 Debug only
Reserved, UNK/SBZP.
ADAdiscard, bit [19], v6.1 Debug and v7 Debug
Asynchronous Data Aborts Discarded bit. The possible values of this bit are:
0 Asynchronous aborts handled normally
1 On an asynchronous abort, the processor sets the Sticky Asynchronous Data
Abort bit, ADABORT_l, to 1 but otherwise discards the abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-13