ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The Saved Program Status Registers (SPSRs)
ARMv6 Differences
The SPSRs are defined as they are in ARMv7, see The Saved Program Status Registers (SPSRs) on
page B1-15, except that the IT[7:0] bits are not implemented before ARMv6T2.
Format of the CPSR and SPSRs
The format of the CPSR and SPSRs is the same as ARMv7:
31 30 29 28 27 26 25 24 23 20 19 16 15 10 9 8 7 6 5 4 0
N Z C V Q IT
[1:0]
J Reserved GE[3:0] IT[7:2] E A I F T M[4:0]
In ARMv6T2, the definitions and general rules for PSR bits and support of Non-Maskable Fast Interrupts
(NMFI) are the same as ARMv7. For more information, see Format of the CPSR and SPSRs on page B1-16
and Non-maskable fast interrupts on page B1-18.
ARMv6 and ARMv6K have the following differences:
Bits[26:25] are RAZ/WI.
Bits[15:10] are reserved.
The J and T bits of the CPSR must not be changed when the CPSR is written by an MSR instruction,
or else the behavior is UNPREDICTABLE. MSR instructions exist only in ARM state in these architecture
variants, so this is equivalent to saying the MSR instructions in privileged modes must treat these bits
as SBZP. MSR instructions in User mode still ignore writes to these bits.
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