ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.219 SWP, SWPB
SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given
by the value of register . The value of register is then stored to the memory address given by the
value of , and the original loaded value is written to register . If the same register is specified for
and , this instruction swaps the value of the register and the value at the memory address.
SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address
given by the value of register . The value of the least significant byte of register is stored to the
memory address given by , the original loaded value is zero-extended to a 32-bit word, and the word is
written to register . If the same register is specified for and , this instruction swaps the value
of the least significant byte of the register and the byte value at the memory address, and clears the most
significant three bytes of the register.
For both instructions, the memory system ensures that no other memory access can occur to the memory
location between the load access and the store access.
Note
The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that
no stores from other observers can occur between the load access and the store access, and this might
not be implemented for all regions of memory on some system implementations. In all cases, SWP and
SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur
between the load access and the store access of the SWP or SWPB.
The use of SWP is deprecated, and new code should use LDREX/STREX in preference to using SWP.
The use of SWPB is deprecated, and new code should use LDREXB/STREXB in preference to using SWPB.
Encoding A1 ARMv4*, ARMv5T*, ARMv6* (deprecated), ARMv7 (deprecated)
SWP{B} ,,[]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 B 0 0 Rn Rt (0)(0)(0)(0) 1 0 0 1 Rt2
t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); size = if B == ‘1’ then 1 else 4;
if t == 15 || t2 == 15 || n == 15 || n == t || n == t2 then UNPREDICTABLE;
A8-432 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B