ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Table B4-8 Summary of CP15 registers in a PMSA implementation (continued)
Register and description
CP15 c13, Context and Thread ID registers on page B4-75
c13, Context ID Register (CONTEXTIDR) on page B4-76
CP15 c13 Software Thread ID registers on page B4-77
CP15 c14 is not used on a PMSA implementation, see Unallocated CP15 encodings on page B4-27
CP15 c15, Implementation defined registers on page B4-78
B4.6.2 General behavior of CP15 registers
The following sections give information about the general behavior of CP15 registers:
Unpredictable and undefined behavior for CP15 accesses
Reset behavior of CP15 registers on page B4-27
See also Meaning of fixed bit values in register diagrams on page B4-29.
Read-only bits in read/write registers
Some read/write registers include bits that are read-only. These bits ignore writes.
An example of this is the SCTLR.NMFI bit, bit [27], see c1, System Control Register (SCTLR) on
page B4-45.
UNPREDICTABLE and UNDEFINED behavior for CP15 accesses
In ARMv7 the following operations are UNDEFINED:
all CDP, MCRR, MRRC, LDC and STC operations to CP15
all CDP2, MCR2, MRC2, MCRR2, MRRC2, LDC2 and STC2 operations to CP15.
Unless otherwise indicated in the individual register descriptions:
reserved fields in registers are UNK/SBZP
reserved values of fields can have UNPREDICTABLE effects.
The following subsections give more information about UNPREDICTABLE and UNDEFINED behavior for
CP15:
Unallocated CP15 encodings on page B4-27
Rules for MCR and MRC accesses to CP15 registers on page B4-27.
B4-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B