ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Recommended External Debug Interface
EDBGRQ
DBGTRIGGER
DBGACK
DBGCPUDONE
1 2 a
Normal state
See the text about the ordering of transition a.
Debug state entry
3 4
Debug state
Figure A-2 Signalling for Debug state entry on an External Debug Request
In Figure A-2 these events must occur in order:
1 The peripheral asserts EBDGRQ and waits for it to be acknowledged.
2 The processor takes the debug event and starts the Debug state entry sequence. The
processor asserts DBGTRIGGER.
3 The processor completes the Debug state entry sequence and asserts DBGACK.
4 The processor completes all Non-debug state memory accesses and asserts
DBGCPUDONE. It might do this only after intervention by an external debugger, see
Asynchronous aborts and entry to Debug state on page C5-5.
Event a, the peripheral deasserting EDBGRQ, can occur at any time after the assertion of EDBGRQ is
acknowledged. In the example shown in Figure A-2, the system is using DBGTRIGGER to acknowledge
EDBGRQ, and therefore event a is not ordered relative to events 3 and 4.
In addition, the processor asserts DBGCPUDONE and DBGACK when the DBGDSCR.DBGack bit is set
to 1, see Debug Status and Control Register (DBGDSCR) on page C10-10.
If the DBGDSCR.DBGack bit is 0, the processor deasserts DBGCPUDONE and DBGACK on exit from
Debug state.
Note
Setting DBGDSCR.DBGack to 1 takes no account of the DBGEN and SPIDEN signals. Setting
DBGDSCR.DBGack to 1 asserts DBGCPUDONE and DBGACK regardless of the security settings.
A v7 Debug implementation of these recommendations might not implement DBGCPUDONE if it would
have identical behavior to DBGACK.
Before v7 Debug, DBGCPUDONE was not part of the recommended external debug interface.
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