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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Events<br />

Note<br />

v6 Debug does not support IVA mismatch breakpoints.<br />

v6.1 Debug <strong>and</strong> v6 Debug do not support address range masks on breakpoints.<br />

IVA comparison programming examples<br />

In all Debug architecture versions, a debugger must configure the BRP so that it matches on all bytes of the<br />

first unit of the instruction, otherwise the generation of Breakpoint debug events is UNPREDICTABLE.<br />

Before <strong>ARM</strong>v6T2, on a processor that implements the Thumb instruction set <strong>and</strong> can take an exception<br />

between the two halfwords of a Thumb BL or BLX (immediate) instruction, a debugger must treat the two<br />

halfwords as separate instructions, <strong>and</strong> set breakpoints on both halfwords. This might require two BRPs.<br />

Note<br />

To ensure compatibility across <strong>ARM</strong>v6 implementations, a debugger can always treat BL or BLX<br />

(immediate) as two instructions when debugging code on an <strong>ARM</strong>v6 processor before <strong>ARM</strong>v6T2.<br />

The examples that follow include setting breakpoints on ThumbEE instructions. These are supported<br />

only in <strong>ARM</strong>v7.<br />

For example, if BRPn <strong>and</strong> BRPm are two breakpoint register pairs, then:<br />

On any <strong>ARM</strong>v6 or <strong>ARM</strong>v7 processor:<br />

— To breakpoint on a Java bytecode at address 0x8001, the debugger must set DBGBVRn to<br />

0x8000 <strong>and</strong> DBGBCRn[8:5] to 0b0010.<br />

— To breakpoint on a 16-bit Thumb or ThumbEE instruction starting at address 0x8002, a<br />

debugger must set DBGBVRn to 0x8000 <strong>and</strong> DBGBCRn[8:5] to 0b1100.<br />

— To breakpoint on an <strong>ARM</strong> instruction starting at address 0x8004, a debugger must set<br />

DBGBVRn to 0x8004 <strong>and</strong> DBGBCRn[8:5] to 0b1111.<br />

On an <strong>ARM</strong>v7 or <strong>ARM</strong>v6T2 processor, a debugger sets breakpoints on a 32-bit Thumb instruction,<br />

or on a 16-bit or a 32-bit ThumbEE instruction, in exactly the same way as on a 16-bit Thumb<br />

instruction. For example:<br />

— To breakpoint on a 16-bit or a 32-bit Thumb or ThumbEE instruction starting at address<br />

0x8000, the debugger must set DBGBVRn to 0x8000 <strong>and</strong> DBGBCRn[8:5] to 0b0011. These are<br />

the settings for breakpointing on any Thumb or ThumbEE instruction, including BL <strong>and</strong> BLX<br />

(immediate).<br />

On an <strong>ARM</strong>v6 or <strong>ARM</strong>v6K processor:<br />

— To breakpoint on a Thumb BL or BLX instruction at address 0x8000, a debugger must set<br />

DBGBVRn to 0x8000, <strong>and</strong> DBGBCRn[8:5] to 0b1111.<br />

— To breakpoint on a Thumb BL or BLX instruction at address 0x8002, a debugger must set<br />

DBGBVRn to 0x8000, DBGBVRm to 0x8004, DBGBCRn[8:5] to 0b1100, <strong>and</strong><br />

DBGBCRm[8:5] to 0b0011.<br />

C3-12 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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