ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VUZP. , Encoded as Q = 1
VUZP. , Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VUZP instruction must be
unconditional.
The data size for the elements of the vectors. It must be one of:
8 encoded as size = 0b00.
16 encoded as size = 0b01.
32 encoded as size = 0b10 for a quadword operation.
Doubleword operation with = 32 is a pseudo-instruction.
, The vectors for a quadword operation.
, The vectors for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
if quadword_operation then
if d == m then
Q[d>>1] = bits(128) UNKNOWN; Q[m>>1] = bits(128) UNKNOWN;
else
zipped_q = Q[m>>1]:Q[d>>1];
for e = 0 to (128 DIV esize) - 1
Elem[Q[d>>1],e,esize] = Elem[zipped_q,2*e,esize];
Elem[Q[m>>1],e,esize] = Elem[zipped_q,2*e+1,esize];
else
if d == m then
D[d] = bits(64) UNKNOWN; D[m] = bits(64) UNKNOWN;
else
zipped_d = D[m]:D[d];
for e = 0 to (64 DIV esize) - 1
Elem[D[d],e,esize] = Elem[zipped_d,2*e,esize];
Elem[D[m],e,esize] = Elem[zipped_d,2*e+1,esize];
Exceptions
Undefined Instruction.
Pseudo-instruction
VUZP.32 , is a synonym for VTRN.32 , .
For details see VTRN on page A8-800.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-805