ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.9.2 c9, Count Enable Set Register (PMCNTENSET)
The Count Enable Set Register, PMCNTENSET, is used to enable:
the Cycle Count Register, PMCCNTR
any implemented event counters, PMNx.
Reading the PMCNTENSET Register shows which counters are enabled. Counters are disabled using the
Count Enable Clear Register, see c9, Count Enable Clear Register (PMCNTENCLR) on page C10-109.
The PMCNTENSET Register is:
a 32-bit read/write CP15 register:
— reading the register shows which counters are enabled
— writing a 1 to a bit of the register enables the corresponding counter
— writing a 0 to a bit of the register has no effect
accessible in:
— privileged modes
— User mode only when the PMUSERENR.EN bit is set to 1
accessed using an MRC or MCR command with set to c9, set to 0, set to c12, and
set to 1.
The format of the PMCNTENSET Register is:
31 30 N N-1 0
C RAZ/WI Event counter enable bits, Px, for x = 0 to (N-1)
Note
In the description of the PMCNTENSET Register:
N is the number of event counters implemented, as defined by the PMCR.N field, see c9,
Performance Monitor Control Register (PMCR) on page C10-105
x refers to a single event counter, and takes values from 0 to (N-1).
C, bit [31] PMCCNTR enable bit.
See Table C10-25 on page C10-109 for the behavior of this bit on reads and writes.
Bits [30:N] RAZ/WI.
Px, bit [x], for x = 0 to (N-1)
Event counter x, PMNx, enable bit.
C10-108 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B