ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
C6.2 Reset and power-down support
This section contains the following subsections:
Debug guidelines for systems with energy management capability
Power domains and debug on page C6-5
The OS Save and Restore mechanism on page C6-8
Recommended reset scheme for v7 Debug on page C6-16.
C6.2.1 Debug guidelines for systems with energy management capability
ARMv7 processors can be built with energy management capabilities. This section describes how to use the
v7 Debug features to debug software running on these systems.
v7 Debug only permits debugging software that is running on a system where:
energy-saving measures are taken only when the processor is in an idle state
it is a function of the operating system, or other supervisor code, to take any implemented
energy-saving measures.
The measures that the OS can take to save energy during an idle state can be split in two groups:
Standby The OS takes some measures, including using IMPLEMENTATION DEFINED features, to
reduce energy consumption. The processor preserves the processor state, including the
debug logic state. Changing from standby to normal operation does not involve a reset of
the processor.
Power-down The OS takes some measures to reduce energy consumption. These measures mean the
processor cannot preserve the processor state, and therefore the measures taken must
include the OS saving any processor state it requires not to be lost. Changing from
power-down to normal operation must include:
a reset of the processor, after the power level has been restored
reinstallation of the processor state by the OS.
Standby is the least invasive OS energy saving state. It implies only that the processor is unavailable, and
does not clear any of the debug settings. For standby, v7 Debug prescribes only the following:
If the processor is in standby and a Halting debug event is triggered the processor must leave standby
to handle the debug event. If the processor executed a WFI or WFE instruction to enter standby then that
instruction is retired.
If the processor is in standby and the external debug or memory-mapped interface is accessed, the
processor must automatically:
— leave standby
— respond to the debug transaction
— go back to standby.
This is possible because the external debug and memory-mapped interface can insert wait states, for
example by holding PREADYDBG LOW, until the processor has left standby.
C6-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B