ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.5 VFP data-processing instructions
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 T 1 1 1 0 opc1 opc2 1 0 1 opc3 0 opc4
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 opc1 opc2 1 0 1 opc3 0 opc4
If T == 1 in the Thumb encoding or cond == 0b1111 in the ARM encoding, the instruction is UNDEFINED.
Otherwise:
Table A7-16 shows the encodings for three-register VFP data-processing instructions. Other
encodings in this space are UNDEFINED.
Table A7-17 on page A7-25 applies only if Table A7-16 indicates that it does. It shows the encodings
for VFP data-processing instructions with two registers or a register and an immediate. Other
encodings in this space are UNDEFINED.
Table A7-18 on page A7-25 shows the immediate constants available in the VMOV (immediate)
instruction.
These instructions are CDP instructions for coprocessors 10 and 11.
opc1 opc3 Instruction See
Table A7-16 Three-register VFP data-processing instructions
0x00 - Vector Multiply Accumulate or Subtract VMLA, VMLS (floating-point) on
page A8-636
0x01 - Vector Negate Multiply Accumulate or Subtract VNMLA, VNMLS, VNMUL on page A8-674
0x10 x1
x0 Vector Multiply VMUL (floating-point) on page A8-664
0x11 x0 Vector Add VADD (integer) on page A8-536
x1 Vector Subtract VSUB (integer) on page A8-788
1x00 x0 Vector Divide VDIV on page A8-590
1x11 - Other VFP data-processing instructions Table A7-17 on page A7-25
A7-24 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B