ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.306 VHADD, VHSUB
Vector Halving Add adds corresponding elements in two vectors of integers, shifts each result right one bit,
and places the final results in the destination vector. The results of the halving operations are truncated (for
rounded results see VRHADD on page A8-734).
Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of
the first operand, shifts each result right one bit, and places the final results in the destination vector. The
results of the halving operations are truncated (there is no rounding version).
The operand and result elements are all the same type, and can be any one of:
8-bit, 16-bit, or 32-bit signed integers
8-bit, 16-bit, or 32-bit unsigned integers.
Encoding T1 / A1 Advanced SIMD
VH , ,
VH , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 0 D size Vn Vd 0 0 op 0 N Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 op 0 N Q M 0 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
if size == ‘11’ then UNDEFINED;
add = (op == ‘0’); unsigned = (U == ‘1’);
esize = 8