ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

occupy the last four words of the 4KB block of debug registers
when the Security Extensions are implemented, are Common registers.
Table C10-24 lists the Debug Component Identification Registers.
Debug Registers Reference
Only bits [7:0] of each Debug Component ID Register are used. This means that the format of each register
is:
31 8 7 0
Reserved, RAZ Component ID data
The four Debug Component ID Registers can be considered as defining a single 32-bit Component ID, as
shown in Figure C10-3. The value of this Component ID is fixed.
Figure C10-3 Mapping between Debug Component ID Registers and the 32-bit Component ID value
The following subsections describe the formats of each of the Debug Component ID Registers.
DBGCID0
Register:
DBGCID0 is debug register 1020 at offset 0xFF0. Its format is:
Bits [31:8] Reserved, RAZ.
Number Offset
Table C10-24 Debug Component Identification Registers
Description Reference
1020 0xFF0 Debug Component ID0 DBGCID0
1021 0xFF4 Debug Component ID1 DBGCID1 on page C10-104
1022 0xFF8 Debug Component ID2 DBGCID2 on page C10-104
1023 0xFFC Debug Component ID3 DBGCID3 on page C10-104
Actual Component ID Register fields
DBGCID3
DBGCID2 DBGCID1 DBGCID0
7 0 7 0 7 0 7
0
1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1
31 16 15 12 11
0
Preamble
Component
class
Preamble
Conceptual 32-bit Component ID
Component ID
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-103