ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The Instruction Sets
A4.7 Load/store multiple instructions
Load Multiple instructions load a subset, or possibly all, of the general-purpose registers from memory.
Store Multiple instructions store a subset, or possibly all, of the general-purpose registers to memory.
The memory locations are consecutive word-aligned words. The addresses used are obtained from a base
register, and can be either above or below the value in the base register. The base register can optionally be
updated by the total size of the data transferred.
Table A4-11 summarizes the load/store multiple instructions in the ARM and Thumb instruction sets.
Instruction See
System level variants of the LDM and STM instructions load and store User mode registers from a privileged
mode. Another system level variant of the LDM instruction performs an exception return. For details, see
Chapter B6 System Instructions.
A4.7.1 Loads to the PC
Table A4-11 Load/store multiple instructions
Load Multiple, Increment After or Full Descending LDM / LDMIA / LDMFD on page A8-110
Load Multiple, Decrement After or Full Ascending a
LDMDA / LDMFA on page A8-112
Load Multiple, Decrement Before or Empty Ascending LDMDB / LDMEA on page A8-114
Load Multiple, Increment Before or Empty Descending a LDMIB / LDMED on page A8-116
Pop multiple registers off the stack b
Push multiple registers onto the stack c
POP on page A8-246
PUSH on page A8-248
Store Multiple, Increment After or Empty Ascending STM / STMIA / STMEA on page A8-374
Store Multiple, Decrement After or Empty Descending a STMDA / STMED on page A8-376
Store Multiple, Decrement Before or Full Descending STMDB / STMFD on page A8-378
Store Multiple, Increment Before or Full Ascending a STMIB / STMFA on page A8-380
a. Not available in the Thumb instruction set.
b. This instruction is equivalent to an LDM instruction with the SP as base register, and base register updating.
c. This instruction is equivalent to an STMDB instruction with the SP as base register, and base register
updating.
The LDM, LDMDA, LDMDB, LDMIB, and POP instructions can be used to load a value into the PC. The value loaded
is treated as an interworking address, as described by the LoadWritePC() pseudocode function in Pseudocode
details of operations on ARM core registers on page A2-12.
A4-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B