ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Exception
offset
Exception that is vectored at that offset from:
Monitor exception base address a
0x00 Not used Reset
The System Level Programmers’ Model
Table B1-3 Offsets from exception base addresses
0x04 Not used Undefined Instruction
a. This column applies only if the Security Extensions are implemented.
Base address for all other exceptions
0x08 Secure Monitor Call (SMC) Supervisor Call (SVC)
0x0C Prefetch Abort Prefetch Abort
0x10 Data Abort Data Abort
0x14 Not used Not used
0x18 IRQ (interrupt) IRQ (interrupt)
0x1C FIQ (fast interrupt) FIQ (fast interrupt)
The default exception vectors for the IRQ and FIQ exceptions can be changed by setting the SCTLR.VE bit
to 1, as described in Vectored interrupt support on page B1-32.
If the Security Extensions are not implemented there is a single exception base address. This is controlled
by the SCTLR.V bit:
V==0 Exception base address = 0x00000000. This setting is referred to as normal vectors, or as low
vectors.
V==1 Exception base address = 0xFFFF0000. This setting is referred to as high vectors, or Hivecs.
Note
Use of the Hivecs setting, V == 1, is deprecated in ARMv7-R. ARM recommends that Hivecs is used only
in ARMv7-A implementations.
If the Security Extensions are implemented there are three exception base addresses:
the Non-secure exception base address is used for all exceptions that are processed in Non-secure
state
the Secure exception base address is used for all exceptions that are processed in Secure state but not
in Monitor mode
the Monitor exception base address is used for all exceptions that are processed in Monitor mode.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-31