ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.8.5 Lock Access Register (DBGLAR)
The Lock Access Register, DBGLAR, provides a lock on writes to the debug registers through the
memory-mapped interface. Use of this lock mechanism reduces the risk of accidental damage to the
contents of the debug registers. It does not, and cannot, prevent all accidental or malicious damage.
You must use the DBGLSR to check the current status of the lock, see Lock Status Register (DBGLSR) on
page C10-95.
The DBGLAR is:
debug register 1004, at offset 0xFB0
a write-only register
only defined in the memory-mapped interface
when the Security Extensions are implemented, a Common register.
Note
Debug register 1004, at offset 0xFB0, is reserved in both the Extended CP14 interface and the external
debug interface.
Do not confuse the Software Lock mechanism with the OS Lock described in The OS Save and
Restore mechanism on page C6-8.
The format of the DBGLAR is:
31 0
Lock Access control
Lock Access control, bits [31:0]
Writing the key value 0xC5ACCE55 to this field clears the lock, enabling write accesses to the
debug registers through the memory-mapped interface.
Writing any other value to this register sets the lock, disabling write accesses to the debug
registers through the memory-mapped interface.
Note
In implementations with separate core and debug power-domains, this lock is maintained in the debug
power domain. Its state is unaffected by the core power domain powering down.
This lock is set on debug logic reset, that is, on a PRESETDBGn or nSYSPORESET reset.
Accesses through the memory-mapped interface to locked debug registers are ignored. For more
information, see Permissions in relation to locks on page C6-27.
C10-94 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B