ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
Table A7-13 Instructions with two registers, miscellaneous (continued)
A B Instruction See
01 x000x Vector Compare Greater Than Zero VCGT (immediate #0) on page A8-562
x001x Vector Compare Greater Than or Equal to Zero VCGE (immediate #0) on page A8-558
x010x Vector Compare Equal to zero VCEQ (immediate #0) on page A8-554
x011x Vector Compare Less Than or Equal to Zero VCLE (immediate #0) on page A8-564
x100x Vector Compare Less Than Zero VCLT (immediate #0) on page A8-568
x110x Vector Absolute VABS on page A8-532
x111x Vector Negate VNEG on page A8-672
0000x Vector Swap VSWP on page A8-796
0001x Vector Transpose VTRN on page A8-800
0010x Vector Unzip VUZP on page A8-804
0011x Vector Zip VZIP on page A8-806
10 01000 Vector Move and Narrow VMOVN on page A8-656
01001 Vector Saturating Move and Unsigned Narrow VQMOVN, VQMOVUN on page A8-708
0101x Vector Saturating Move and Narrow VQMOVN, VQMOVUN on page A8-708
01100 Vector Shift Left Long (maximum shift) VSHLL on page A8-754
11x00 Vector Convert VCVT (between half-precision and
single-precision, Advanced SIMD) on
page A8-586
11 10x0x Vector Reciprocal Estimate VRECPE on page A8-728
10x1x Vector Reciprocal Square Root Estimate VRSQRTE on page A8-742
11xxx Vector Convert VCVT (between floating-point and integer,
Advanced SIMD) on page A8-576
A7-20 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B