05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Debug Registers <strong>Reference</strong><br />

C10.9.9 c9, Event Count Register (PMXEVCNTR)<br />

The Event Count Register, PMXEVCNTR, is used to read or write the value of the current event counter,<br />

PMNx. PMSELR selects the current event counter, see c9, Event Counter Selection Register (PMSELR) on<br />

page C10-113.<br />

The PMXEVCNTR is:<br />

a 32-bit read/write CP15 register<br />

accessible in:<br />

— privileged modes<br />

— User mode only when the PMUSERENR.EN bit is set to 1<br />

when the Security Extensions are implemented, a Common register<br />

accessed using an MRC or MCR comm<strong>and</strong> with set to c9, set to 0, set to c13, <strong>and</strong><br />

set to 2.<br />

The format of the PMXEVCNTR is:<br />

31 0<br />

PMNX<br />

PMNX, bits [31:0]<br />

Value of the current event counter, PMNx.<br />

A read of the PMXEVCNTR always returns the current value of the register.<br />

The contents of each of the Event Count Registers are UNKNOWN on a core logic reset.<br />

Note<br />

You can write to the PMXEVCNTR even when the counter is disabled. This is true regardless of why the<br />

counter is disabled, which can be any of:<br />

because 1 has been written to the appropriate bit in the PMCNTENCLR<br />

because the PMCR.E bit is set to 0<br />

by the non-invasive debug authentication.<br />

C10-116 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!