ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
H.6.4 Protected memory support
The MPU based Protected Memory System Architecture (PMSA) is a much simpler memory protection
scheme than the MMU-based VMSA model described in Virtual memory support on page AppxH-21. The
simplification applies to both the hardware and the software. PMSA in ARMv4 and ARMv5 differs from
that supported in ARMv6 and ARMv7 in the following ways:
the programming model is unique to ARMv4 and ARMv5
the supported number of memory regions is fixed
background memory support requires use of a region resource
there is no architecturally-defined recovery mechanism from memory aborts
there is no default memory map definition.
Control and configuration
CP15 registers are used to fully define protection regions, eliminating the VMSA requirements for hardware
to do translation table walks, and for software to set up and maintain the translation tables. This makes
memory checking fully deterministic. However, the level of control is now region based rather than page
based. This means the control is not as fine-grained.
The following features apply:
The memory is divided into regions. CP15 registers are used to define the region size, base address,
and memory attributes. For example, cacheability, bufferability, and access permissions of a region.
Memory region control (read and write access) is permitted only from privileged modes.
If an address is defined in multiple regions, a fixed priority scheme (highest region number) is used
to define the properties of the address being accessed.
An access to an address that is not defined in any region causes a memory abort.
All addresses are physical addresses. Address translation is not supported.
PMSA supports unified (von Neumann) and separate (Harvard) instruction and data address spaces.
Eight regions can be configured, with C, B, and AP[1:0] attribute bits associated with each region. The
supported region sizes are 2NKB, where 2 =< N =< 32. It is IMPLEMENTATION DEFINED if the regions are
configurable or fixed in an implementation:
as eight unified regions supporting data accesses and instruction fetches
as eight data regions and eight instruction regions each with independent memory region attributes.
CP15 provides the following support:
a global MPU enable bit, SCTLR.M
cacheability register support, a C bit for each region
bufferability register support, a B bit for each region
AppxH-28 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B