ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register In a Description, see
Register Index
Auxiliary Fault Status PMSA c5, Auxiliary Data and Instruction Fault Status Registers (ADFSR and
AIFSR) on page B4-56
VMSA c5, Auxiliary Data and Instruction Fault Status Registers (ADFSR and
AIFSR) on page B3-123
Auxiliary Feature 0 c0, Auxiliary Feature Register 0 (ID_AFR0) on page B5-8
Auxiliary ID PMSA c0, Implementation defined Auxiliary ID Register (AIDR) on page B4-43
VMSA c0, Implementation defined Auxiliary ID Register (AIDR) on page B3-94
Block Transfer Status, ARMv6 c7, Block Transfer Status Register on page AppxG-43
BPIALL PMSA CP15 c7, Cache and branch predictor maintenance functions on
page B4-68
VMSA CP15 c7, Cache and branch predictor maintenance functions on
page B3-126
BPIALLIS PMSA CP15 c7, Cache and branch predictor maintenance functions on
page B4-68
VMSA CP15 c7, Cache and branch predictor maintenance functions on
page B3-126
BPIMVA PMSA CP15 c7, Cache and branch predictor maintenance functions on
page B4-68
VMSA CP15 c7, Cache and branch predictor maintenance functions on
page B3-126
Breakpoint Control Breakpoint Control Registers (DBGBCR) on page C10-49
Breakpoint value Breakpoint Value Registers (DBGBVR) on page C10-48
c0 - c15 Generic Instruction descriptions of the CDP, CDP2, LDC, LDC2, MCR, MCR2, MCRR, MCRR2,
MRC, MRC2, MRRC, MRRC2, STC, and STC2 generic coprocessor instructions.
Cache Behavior Override, ARMv6
Security Extensions
Table K-1 Register index (continued)
PMSA Summary of CP15 register descriptions in a PMSA implementation on
page B4-24
VMSA Summary of CP15 register descriptions in a VMSA implementation on
page B3-66
c9, Cache Behavior Override Register (CBOR) on page AppxG-49
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxK-3