ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
CP15
register
Banked CP15 registers
When the Security Extensions are implemented, some CP15 registers are banked. Banked CP15 registers
have two copies, one Secure and one Non-secure. The SCR.NS bit selects the Secure or Non-secure register,
see c1, Secure Configuration Register (SCR) on page B3-106. Table B3-15 shows which registers are
banked, and the permitted access to each register.
Banked register Permitted accessesa
Table B3-15 Banked CP15 registers
c0 CSSELR, Cache Size Selection Register Read/write in privileged modes only
c1 SCTLR, System Control Register b Read/write in privileged modes only
ACTLR, Auxiliary Control Register c Read/write in privileged modes only
c2 TTBR0, Translation Table Base 0 Read/write in privileged modes only
TTBR1, Translation Table Base 1 Read/write in privileged modes only
TTBCR, Translation Table Base Control Read/write in privileged modes only
c3 DACR, Domain Access Control Register Read/write in privileged modes only
c5 DFSR, Data Fault Status Register Read/write in privileged modes only
IFSR, Instruction Fault Status Register Read/write in privileged modes only
ADFSR, Auxiliary Data Fault Status Register c Read/write in privileged modes only
AIFSR, Auxiliary Instruction Fault Status Register c Read/write in privileged modes only
c6 DFAR, Data Fault Address Register Read/write in privileged modes only
IFAR, Instruction Fault Address Register Read/write in privileged modes only
c7 PAR, Physical Address Register (VA to PA translation) Read/write in privileged modes only
c10 PRRR, Primary Region Remap Register Read/write in privileged modes only
NMRR, Normal Memory Remap Register Read/write in privileged modes only
c12 VBAR, Vector Base Address Register Read/write in privileged modes only
B3-72 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B