ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
ARMv6 Differences
When an implementation does not include the CFGEND[1:0] signal, a value of 0b00 is assumed.
ARMv6 does not support the static instruction endianness configuration feature described in Instruction
endianness static configuration, ARMv7-R only on page A3-9.
G.6.2 Cache support
CFGEND[1:0]
ARMv7 can detect and manage a multi-level cache topology. ARMv6 only detects and manages level 1
caches, and the cache type is stored in the Cache Type Register. See c0, Cache Type Register (CTR) on
page AppxH-35.
In ARMv6, the L1 cache must appear to software to behave as follows:
Table G-3 Configuration options on reset
CP15 System Control Register, SCTLR PSR
EE bit U bit A bit B bit E bit
00 0 0 0 0 0
01 a
0 0 0 1 0
10 0 1 0 0 0
11 1 1 0 0 1
a. This configuration is reserved in implementations that do not support BE-32. In
this case, the B bit is RAZ.
the entries in the cache do not need to be cleaned, invalidated, or cleaned and invalidated by software
for different virtual to physical mappings
for memory regions that are described in the page tables as being Cacheable, aliases to the same
physical address can exist, subject to the restrictions for 4KB small pages described in Virtual to
physical translation mapping restrictions on page AppxG-26.
Note
These requirements are different from the required ARMv7 cache behavior described in Address mapping
restrictions on page B3-23.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-21