ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
ARMv6 Differences
This appendix describes the instructions included as a mnemonic in ARMv6. For any mnemonic, to
determine which associated instruction encodings appear in a particular architecture variant, see the
subsections of Alphabetical list of instructions on page A8-14 that describe the mnemonic. Each encoding
diagram shows the architecture variants or extensions that include the encoding.
The following sections give more information about ARMv6 instruction set support:
ARM instruction set support
Thumb instruction set support on page AppxG-14
System level instruction set support on page AppxG-14.
G.4.1 ARM instruction set support
ARMv6 includes all the ARM instructions present in ARMv5TEJ, see ARM instruction set support on
page AppxH-12. Table G-2 shows the ARM instruction changes in the ARMv6 base architecture.
Table G-2 ARM instruction changes in ARMv6
Instruction ARMv6 change
CPS Introduced
LDREX Introduced
MCRR2 Introduced
MRRC2 Introduced
PKH Introduced
QADD16 Introduced
QADD8 Introduced
QASX Introduced
QSUB16 Introduced
QSUB8 Introduced
QSAX Introduced
REV, REV16, REVSH Introduced
RFE Introduced
SADD8, SADD16, SASX Introduced
SEL Introduced
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-11