ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Exception Base LR value a
Instruction set state on exception entry
The System Level Programmers’ Model
Prefetch Abort Address of aborted instruction fetch + 4 +4 + 4
Data Abort Address of instruction that generated
the abort
Table B1-4 Link Register value saved on exception entry (continued)
Offset, for processor state of: a
ARM Thumb or ThumbEE Jazelle
+ 8 +8 + 8
IRQ or FIQ Address of next instruction to execute + 4 +4 + 4
a. Except for the Reset exception, the value saved in the LR is the base LR value plus the offset value for the processor
state immediately before the exception entry.
b. In Jazelle state, Undefined Instruction exceptions can only happen on a processor that includes a trivial implementation
of Jazelle state. On such a processor, if an exception return instruction writes {CPSR.J, CPSR.T} to 0b10, the processor
takes an Undefined Instruction exception when it next attempts to execute an instruction. It is IMPLEMENTATION
DEFINED whether the processor uses an offset of +2 or +4 in these circumstances, but it must always use the same offset.
c. SVC and SMC exceptions cannot occur in Jazelle state.
Exception handlers always execute in either Thumb state or ARM state. Which state they execute in is
determined by the Thumb Exception enable bit, SCTLR.TE, see:
c1, System Control Register (SCTLR) on page B3-96 for a VMSA implementation
c1, System Control Register (SCTLR) on page B4-45 for a PMSA implementation.
On exception entry, the CPSR.T and CPSR.J bits are set to values that depend on the SCTLR.TE value, as
shown in Table B1-5:
Table B1-5 CPSR.J and CPSR.T bit values on exception entry
SCTLR.TE CPSR.J CPSR.T Exception handler state
0 0 0 ARM
1 0 1 Thumb
When the Security Extensions are implemented, the SCTLR is banked for Secure and Non-secure states,
and therefore the TE bit value might be different for Secure and Non-secure states. The SCTLR.TE bit for
the security state in which the exception is handled determines the instruction set state for the exception
handler. This means the exception handlers might run in different instruction set states, depending on the
security state.
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