ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B4.6.13 c0, IMPLEMENTATION DEFINED Auxiliary ID Register (AIDR)
Protected Memory System Architecture (PMSA)
The IMPLEMENTATION DEFINED Auxiliary ID Register, AIDR, provides implementation-specific ID
information. The value of this register must be used in conjunction with the value of the MIDR.
The IMPLEMENTATION DEFINED AIDR is:
a 32-bit read-only register
accessible only in privileged modes
introduced in ARMv7.
The format of the AIDR is IMPLEMENTATION DEFINED.
Accessing the AIDR
To access the AIDR you read the CP15 registers with set to 1, set to c0, set to c0, and
set to 7. For example:
MRC p15,1,,c0,c0,7 ; Read IMPLEMENTATION DEFINED Auxiliary ID Register
B4.6.14 c0, Cache Size Selection Register (CSSELR)
The Cache Size Selection Register, CSSELR, selects the current CCSIDR. An ARMv7 implementation
must include a CCSIDR for every implemented cache that is under the control of the processor. The
CSSELR identifies which CCSIDR can be accessed, by specifying, for the required cache:
the cache level
the cache type, either:
— instruction cache.
— Data cache. The data cache argument is also used for a unified cache.
CSSELR is:
a 32-bit read/write register
accessible only in privileged modes
introduced in ARMv7.
The format of the CSSELR is:
31 4 3
1
Bits [31:4] UNK/SBZP.
Level, bits [3:1]
UNK/SBZP
Cache level of required cache. Permitted values are from 0b000, indicating Level 1 cache,
to 0b110 indicating Level 7 cache.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-43
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