ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Change Processor State, and hints
Thumb Instruction Set Encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 0 1 0 0 op1 op2
Table A6-14 shows the allocation of encodings in this space. Other encodings in this space are unallocated
hints that execute as NOPs. These unallocated hint encodings are reserved and software must not use them.
Miscellaneous control instructions
Table A6-14 Change Processor State, and hint instructions
op1 op2 Instruction See Variant
not 000 - Change Processor State CPS on page B6-3 v6T2
000 00000000 No Operation hint NOP on page A8-222 v6T2
00000001 Yield hint YIELD on page A8-812 v7
00000010 Wait For Event hint WFE on page A8-808 v7
00000011 Wait For Interrupt hint WFI on page A8-810 v7
00000100 Send Event hint SEV on page A8-316 v7
1111xxxx Debug hint DBG on page A8-88 v7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 1 1 0 0 op
Table A6-15 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED
in ARMv7. They are UNPREDICTABLE in ARMv6.
Table A6-15 Miscellaneous control instructions
op Instruction See Variant
0000 Leave ThumbEE state a ENTERX, LEAVEX on page A9-7 ThumbEE
0001 Enter ThumbEE state ENTERX, LEAVEX on page A9-7 ThumbEE
0010 Clear-Exclusive CLREX on page A8-70 v7
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A6-21