ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
When nU == 0 this field is reserved, UNK.
D_nlock, bits [15:8] Number of lockable entries in the data TLB. The value of this field gives the number
of lockable entries, between 0b00000000 for no lockable entries, and 0b11111111
for 255 lockable entries.
nU, bit [0] Not Unified TLB. Indicates whether the implementation has a unified TLB:
nU == 0 Unified TLB.
nU == 1 Separate instruction and data TLBs.
G.7.4 c1, System control support
ARMv6 implements the same system control registers as ARMv7:
for a VMSA implementation, see CP15 c1, System control registers on page B3-96
for a PMSA implementation, see CP15 c1, System control registers on page B4-44.
c1, System Control Register (SCTLR)
This register is the primary system configuration register in CP15. It is defined differently for VMSA and
PMSA.
In a VMSAv6 implementation, the format of the SCTLR is:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(0) (0)(0)
U 0 0 1 (0) 1 V I Z (0) R S B 1 1 1 W C A M
TE
L2 VE
NMFI EE XP
FI
RR
L4
In an ARMv6K VMSA implementation, the format of the SCTLR is:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(0)
U 0 0 1 1 V I Z (0) R S B 1 1 1 W C A M
TE TRE L2 VE FI HA RR
AFE EE XP L4
NMFI
Note
Where the Security Extensions are implemented, some SCTLR bits are banked as described in c1, System
Control Register (SCTLR) on page B3-96.
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