ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
if HaveSecurityExt() then SCR.NS = ‘0’;
ResetCP15Registers();
ResetDebugRegisters();
if HaveAdvSIMDorVFP() then FPEXC.EN = ‘0’; SUBARCHITECTURE_DEFINED further resetting;
if HaveThumbEE() then TEECR.XED = ‘0’;
if HaveJazelle() then JMCR.JE = ‘0’; SUBARCHITECTURE_DEFINED further resetting;
// Further CPSR changes: all interrupts disabled, IT state reset, instruction set
// and endianness according to the SCTLR values produced by the above call to
// ResetCP15Registers().
CPSR.I = ‘1’; CPSR.F = ‘1’; CPSR.A = ‘1’;
CPSR.IT = ‘00000000’;
CPSR.J = ‘0’; CPSR.T = SCTLR.TE; // TE=0: ARM, TE=1: Thumb
CPSR.E = SCTLR.EE; // EE=0: little-endian, EE=1: big-endian
// All registers, bits and fields not reset by the above pseudocode or by the
// BranchTo() call below are UNKNOWN bitstrings after reset. In particular, the
// return information registers R14_svc and SPSR_svc have UNKNOWN values, so that
// it is impossible to return from a reset in an architecturally defined way.
// Branch to Reset vector.
BranchTo(ExcVectorBase() + 0);
The ARM architecture does not define any way of returning from a reset.
B1.6.11 Undefined Instruction exception
An Undefined Instruction exception might be caused by:
a coprocessor instruction that is not accessible because of the settings in one or both of:
— the Coprocessor Access Control Register, see c1, Coprocessor Access Control Register
(CPACR) on page B3-104 for a VMSA implementation, or c1, Coprocessor Access Control
Register (CPACR) on page B4-51 for a PMSA implementation
— in an implementation that includes the Security Extensions, the Non-Secure Access Control
Register, see c1, Non-Secure Access Control Register (NSACR) on page B3-110
a coprocessor instruction that is not implemented
an instruction that is UNDEFINED
an attempt to execute an instruction in an unsupported instruction set state, see Exception return to
an unsupported instruction set state on page B1-40
division by zero in an SDIV or UDIV instruction in the ARMv7-R profile when the SCTLR.DZ bit is set
to 1, see c1, System Control Register (SCTLR) on page B4-45.
The Undefined Instruction exception can be used for:
software emulation of a coprocessor in a system that does not have the physical coprocessor hardware
lazy context switching of coprocessor registers
general-purpose instruction set extension by software emulation
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-49