ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Swap_instrs, bits [3:0]
The CPUID Identification Scheme
Indicates the supported Swap instructions in the ARM instruction set. Permitted values are:
0b0000 None supported.
0b0001 Adds support for SWP and SWPB.
c0, Instruction Set Attribute Register 1 (ID_ISAR1)
The format of the IID_ISAR1 is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
Jazelle
_instrs
Interwork
_instrs
Jazelle_instrs, bits [31:28]
Indicates the supported Jazelle extension instructions. Permitted values are:
0b0000 No support for Jazelle.
0b0001 Adds support for BXJ instruction, and the J bit in the PSR.
This setting might indicate a trivial implementation of Jazelle support.
Interwork_instrs, bits [27:24]
Indicates the supported Interworking instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for BX instruction, and the T bit in the PSR.
0b0010 As for 0b0001, and adds support for BLX instruction. PC loads have BX-like
behavior.
0b0011 As for 0b0010, but guarantees that data-processing instructions in the ARM
instruction set with the PC as the destination and the S bit clear have BX-like
behavior.
Note
Immediate
_instrs
IfThen
_instrs
Extend
_instrs
Except_AR
_instrs
Except
_instrs
Endian
_instrs
A value of 0b0000, 0b0001, or 0b0010 in this field does not guarantee that an ARM
data-processing instruction with the PC as the destination and the S bit clear behaves like an
old MOV PC instruction, ignoring bits [1:0] of the result. With these values of this field:
if bits [1:0] of the result value are 0b00 then the processor remains in ARM state
if bits [1:0] are 0b01, 0b10 or 0b11, the result must be treated as UNPREDICTABLE.
Immediate_instrs, bits [23:20]
Indicates the support for data-processing instructions with long immediates. Permitted
values are:
0b0000 None supported.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-25