ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.4.4 Signed multiplies
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 1 1 1 0 op1 A op2 1
Table A5-20 shows the allocation of encodings in this space. These encodings are all available in ARMv6T2
and above, and are UNDEFINED in earlier variants of the architecture.
Other encodings in this space are UNDEFINED.
Table A5-20 Signed multiply instructions
op1 op2 A Instruction See
000 00x not 1111 Signed Multiply Accumulate Dual SMLAD on page A8-332
1111 Signed Dual Multiply Add SMUAD on page A8-352
01x not 1111 Signed Multiply Subtract Dual SMLSD on page A8-342
1111 Signed Dual Multiply Subtract SMUSD on page A8-360
100 00x - Signed Multiply Accumulate Long Dual SMLALD on page A8-338
01x - Signed Multiply Subtract Long Dual SMLSLD on page A8-344
101 00x not 1111 Signed Most Significant Word Multiply Accumulate SMMLA on page A8-346
1111 Signed Most Significant Word Multiply SMMUL on page A8-350
11x - Signed Most Significant Word Multiply Subtract SMMLS on page A8-348
A5-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B