ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CP15 c8 TLB maintenance functions:
are write-only operations
can be executed only in privileged modes.
Table B3-35 summarizes the TLB maintenance operations.
Virtual Memory System Architecture (VMSA)
Table B3-35 CP15 c8 TLB maintenance operations
CRm opc2 Mnemonic Function Rt data
c3 0 TLBIALLIS Invalidate entire unified TLB d Inner Shareable a Ignored
1 TLBIMVAIS Invalidate unified TLB d entry by MVA Inner Shareable a MVA
2 TLBIASIDIS Invalidate unified TLB d by ASID match Inner Shareable a ASID
3 TLBIMVAAIS Invalidate unified TLB d entry by MVA all ASID Inner
Shareable a
c5 0 ITLBIALL Invalidate entire instruction TLB b Ignored
For more information about the Inner Shareable operations see Multiprocessor effects on TLB maintenance
operations on page B3-62.
For information about the effect of these operations on locked TLB entries see The interaction of TLB
maintenance operations with TLB lockdown on page B3-57.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-139
MVA
1 ITLBIMVA Invalidate instruction TLB b entry by MVA MVA
2 ITLBIASID Invalidate instruction TLB b by ASID match ASID
c6 0 DTLBIALL Invalidate entire data TLB b Ignored
1 DTLBIMVA Invalidate data TLB b entry by MVA MVA
2 DTLBIASID Invalidate data TLB b by ASID match ASID
c7 0 TLBIALL c Invalidate entire unified TLB d Ignore
1 TLBIMVA c Invalidate unified TLB d entry by MVA MVA
2 TLBIASID c Invalidate unified TLB d by ASID match ASID
3 TLBIMVAA Invalidate unified TLB d entries by MVA all ASID a MVA
a. Implemented only as part of the Multiprocessing Extensions.
b. If these operations are performed on an implementation that has a unified TLB they operate on the unified TLB.
c. The mnemonics for the operations with CRm==c7, opc2=={0,1,2} were previously UTLBIALL, UTLBIMVA and
UTLBIMASID.
d. When separate instruction and data TLBs are implemented, these operations are performed on both TLBs.