ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.400 VSTR
This instruction stores a single extension register to memory, using an address from an ARM core register,
with an optional offset.
Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
VSTR , [{, #+/-}]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 1 U D 0 0 Rn Vd 1 0 1 1 imm8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 1 U D 0 0 Rn Vd 1 0 1 1 imm8
single_reg = FALSE; add = (U == ‘1’); imm32 = ZeroExtend(imm8:’00’, 32);
d = UInt(D:Vd); n = UInt(Rn);
if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
Encoding T2 / A2 VFPv2, VFPv3
VSTR , [{, #+/-}]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 1 U D 0 0 Rn Vd 1 0 1 0 imm8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 1 U D 0 0 Rn Vd 1 0 1 0 imm8
single_reg = TRUE; add = (U == ‘1’); imm32 = ZeroExtend(imm8:’00’, 32);
d = UInt(Vd:D); n = UInt(Rn);
if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
A8-786 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B