ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Table C10-11 Effect of byte address selection on Breakpoint generation (continued)
Jazelle DBGBVR:’11’ 1xxx Hit Miss
In a processor with a trivial implementation of the Jazelle extension, generation of Breakpoint debug events
is UNPREDICTABLE, and the value of a subsequent read from DBGBCR[8:5] is UNKNOWN, if the value
written to DBGBCR[8:5] has either DBGBCR[8] != DBGBCR[7], or DBGBCR[6] != DBGBCR[5]. For a
description of the trivial implementation of the Jazelle extension see Trivial implementation of the Jazelle
extension on page B1-81.
Note
0xxx Miss Hit
Any other address xxxx Miss Hit
a. As indicated by the CPSR.J and CPSR.T bits.
b. For more information see the Note that follows this table.
This BRP programmed for:
Instruction set a Instruction address b DBGBCR[8:5] IVA match IVA mismatch
In Table C10-11 on page C10-56, the instruction address value is the address of the first unit of the
instruction. For more information, including what happens when the BRP hits the address of a unit
of the instruction other than the first unit, see IVA comparisons and instruction length on page C3-10.
In the ARMv7-R profile, the value of the Instruction Endianness bit, SCTLR.IE, does not affect the
generation of breakpoint debug events. For more information about instruction endianness, see
Instruction endianness on page A3-8.
For examples of how to program a BRP using byte address selection see IVA comparison programming
examples on page C3-12.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-57