ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Exception
The System Level Programmers’ Model
Table B1-7 A and F bit values on exception entry, with Security Extensions and NS == 0
SCR bits
NS == 0, Secure
Exception mode
EA IRQ FIQ CPSR.A CPSR.F
Reset x x x Supervisor 1 1
Undefined Instruction x x x Undefined Unchanged Unchanged
Supervisor Call (SVC) x x x Supervisor Unchanged Unchanged
Secure Monitor Call (SMC) x x x Monitor 1 1
All external aborts
0 x x Abort 1 Unchanged
1 x x Monitor 1 1
All internal aborts x x x Abort 1 Unchanged
IRQ
FIQ
Exception
x 0 x IRQ 1 Unchanged
x 1 x Monitor 1 1
x x 0 FIQ 1 1
x x 1 Monitor 1 1
Table B1-8 A and F bit values on exception entry, with Security Extensions and NS == 1
SCR bits
Exception
NS == 1, Non-secure
EA IRQ FIQ AW FW
mode
CPSR.A CPSR.F
Reset x x x x x Supervisor 1 1
Undefined Instruction x x x x x Undefined Unchanged Unchanged
Supervisor Call (SVC) x x x x x Supervisor Unchanged Unchanged
Secure Monitor Call (SMC) x x x x x Monitor 1 1
All external aborts
0 x x 0 x Abort Unchanged Unchanged
0 x x 1 x Abort 1 Unchanged
1 x x x x Monitor 1 1
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-37