ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Permitted IMPLEMENTATION DEFINED limits
Debug Registers Reference
The DBGDSMCR is required. However, there can be IMPLEMENTATION DEFINED limits on its behavior.
Table C10-19 lists six permitted options for implementations. Some of these options are orthogonal.
Limit Description Notes
Full
DBGDSMCR
No I-TLB
controls
Table C10-19 Permitted IMPLEMENTATION DEFINED limits on DBGDSCCR behavior
Bits [3:0]
implemented
Bits [3,1] are
RAZ/WI
Unified TLB Bits [3,1] are
RAZ/WI
No matching
control
TLB evictions
always enabled
No loading
control
Bits [3:2] are
RAZ/WI
-
Instruction cache linefill and eviction disable features not implemented.
Instruction fetches disabled in Debug state. For most implementations no TLB
accesses take place in Debug state, and nIUL and nIUM are not required.
-
The TLB matching controls are not used to reduce the impact of debugging, only
for advanced debugging features. If not implemented, these bits are RAZ,
although the processor behaves as if they were set to 1.
- nIUL and nDUL disable TLB loading in Debug state. However TLB evictions
can still take place even when these control bits are set to 0.
Bits [1:0] are
RAZ/WI
-
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-87