ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SCTLR a
S R
ARMv4 and ARMv5 Differences
access permissions using the AP[1:0], SCTLR.S and SCTLR.R bits as defined in Table H-6 on
page AppxH-23
from ARMv5TE, the option of marking sections as Shareable and support for extended cache
attributes using the TEX bitfield with the C and B bits. See Table H-7 and Table H-8 on
page AppxH-25.
AP[1:0]
Note
Privileged
permissions
Table H-6 VMSA access permissions in ARMv4 and ARMv5
User
permissions
Description
0 0 00 No access No access All accesses generate Permission faults
x x 01 Read/write No access Privileged access only
x x 10 Read/write Read-only Writes in User mode generate Permission faults
x x 11 Read/write Read/write Full access
0 1 00 Read-only Read-only Read-only in privileged and User modes
1 0 00 Read-only No access Privileged read-only
1 1 00 - - Reserved
a. For more information, see c1, System Control Register (SCTLR) on page AppxH-39.
Changes to the S and R bits do not affect the access permissions of entries already in the TLB. The TLB
must be flushed for the updated S and R bit values to take effect.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-23