ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.75 LDRH (literal)
Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a
halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information
about memory accesses see Memory accesses on page A8-13.
Encoding T1
LDRH ,
ARMv6T2, ARMv7
LDRH ,[PC,#-0] Special case
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 U 0 1 1 1 1 1 1 Rt imm12
if Rt == ‘1111’ then SEE “Unallocated memory hints”;
t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ‘1’);
if t == 13 then UNPREDICTABLE;
Encoding A1
LDRH ,
ARMv4*, ARMv5T*, ARMv6*, ARMv7
LDRH ,[PC,#-0] Special case
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 (1) U 1 (0) 1 1 1 1 1 Rt imm4H 1 0 1 1 imm4L
t = UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == ‘1’);
if t == 15 then UNPREDICTABLE;
Unallocated memory hints See Load halfword, memory hints on page A6-26
A8-154 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B