ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

H.7.7 c2, c3, c5, and c6, PMSA support
ARMv4 and ARMv5 Differences
While the general principles for memory protection in ARMv4 and ARMv5 are the same, CP15 support for
protected memory is different from the programming model of ARMv6 and ARMv7. Memory regions have
configurable base address and size attributes. There are also registers for describing cacheability,
bufferability, and access permissions across the regions. For more information, see Memory model and
memory ordering on page AppxH-10.
ARMv4 and ARMv5 support a fixed number of memory regions, either:
eight unified memory regions
eight data and eight instruction regions.
Table H-19 shows the PMSA register support.
Table H-19 PMSA register support
Register CRn opc1 CRm opc2
Data or unified Cacheability Register, DCR c2 0 c0 0
Instruction Cacheability Register, ICR c2 0 c0 1
Data or unified Bufferability Register, DBR c3 0 c0 0
Data or unified Access Permission Register, DAPR c5 0 c0 0
Instruction Access Permission Register, IAPR c5 0 c0 1
Data or unified Extended Access Permission Register, DEAPR c5 0 c0 2
Instruction Extended Access Permission Register, IEAPR c5 0 c0 3
Data or unified Memory Region Registers, DMRR0-DMRR7 c6 0 c0-c7 a 0
Instruction Memory Region Registers, IMRR0-IMRR7 c6 0 c0-c7 a 1
a. selects the region, for example == 6 selects the region register for region 6, DMRR6 or IMRR6.
If an implementation has a single set of protection regions that apply to both instruction and data accesses,
only the registers that are accessed using even values of exist. Where separate data and instruction
regions are supported, with the exception of the extended access permission registers, registers associated
with data have == 0 and those associated with instructions have == 1. All PMSA registers are
32-bit registers and only accessible in privileged modes.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-43