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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Events<br />

For each of the memory hint instructions, PLD <strong>and</strong> PLI, it is IMPLEMENTATION DEFINED whether the<br />

instruction generates Watchpoint debug events. If either or both of the PLD <strong>and</strong> PLI instructions normally<br />

generates Watchpoint debug events, the behavior must be:<br />

For the PLI instruction:<br />

— no watchpoint is generated in a situation where, if the instruction was a real fetch rather than<br />

a hint, the real fetch would generate a Prefetch Abort exception<br />

— in all other situations a Watchpoint debug event is generated.<br />

For the PLD instruction:<br />

— no watchpoint is generated in a situation where, if the instruction was a real memory access<br />

rather than a hint, the real memory access would generate a Data Abort exception<br />

— in all other situations a Watchpoint debug event is generated.<br />

When watchpoint generation is conditional on the type of memory access, a memory hint instruction<br />

is treated as generating a load access.<br />

It is IMPLEMENTATION DEFINED whether the following cache maintenance operations generate Watchpoint<br />

debug events:<br />

Clean data or unified cache line by MVA to PoU, DCCMVAU<br />

Clean data or unified cache line by MVA to PoC, DCCMVAC<br />

Invalidate data or unified cache line by MVA to PoC, DCIMVAC<br />

Invalidate instruction cache line by MVA to PoU, ICIMVAU<br />

Clean <strong>and</strong> Invalidate data or unified cache line by MVA to PoC, DCCIMVAC.<br />

When Watchpoint debug event generation by these cache maintenance operations is implemented, the<br />

behavior must be:<br />

the cache maintenance operation must generate a Watchpoint debug event on a DVA match,<br />

regardless of whether the data is stored in any cache<br />

when watchpoint generation is conditional on the type of memory access, a cache maintenance<br />

operation is treated as generating a store access.<br />

For regular data accesses, the size of the access is considered when determining whether a watched byte is<br />

being accessed. The size of the access is IMPLEMENTATION DEFINED for:<br />

memory hint instructions, PLD <strong>and</strong> PLI<br />

cache maintenance operations.<br />

Watchpoint debug events are precise <strong>and</strong> can be synchronous or asynchronous:<br />

a synchronous Watchpoint debug event acts like a synchronous abort exception on the memory access<br />

instruction itself<br />

an asynchronous Watchpoint debug event acts like a precise asynchronous abort exception that<br />

cancels a later instruction.<br />

For more information, see Synchronous <strong>and</strong> Asynchronous Watchpoint debug events on page C3-18.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. C3-17

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