ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

c6, Memory Region registers (DMRR0-DMRR7 and IMRR0-IMRR7)
The Memory Region registers define the MPU memory regions as follows:
ARMv4 and ARMv5 Differences
If an implementation supports only a single set of memory region definitions that apply to both data
and instruction accesses, it must provide a single set of eight Data or unified Memory Region
Registers, DMRR0-DMRR7.
If an implementation supports separate memory region definitions for data and instruction accesses,
it must provide two sets of eight Memory Region Registers:
— eight Data or unified Memory Region Registers, DMRR0-DMRR7
— eight Instruction Memory Region Registers, IMRR0-IMRR7.
Each Memory Region register:
defines a single memory region by specifying its base address and size
includes an enable bit for the associated memory region.
The format of a Memory Region register is:
31 12 11 6 5 1 0
Region base address, bits [31:12]
Bits [31:12] of the base address for the region. Bits [11:0] of the address must be zero.
Therefore, the smallest region that can be defined is 4KB. Regions must be aligned
appropriately, and so for regions larger than 4KB the least significant bits of this field must
be zero. For more information, see the description of the Size field.
Bits [11:6] Reserved. UNK/SBZP.
Size, bits [5:1]
Region base address Reserved Size En
Encodes the size of the region. Table H-20 shows the permitted encodings for this field.
Table H-20 MPU Region size encoding
Encoding Region size Base address constraints
0b01011 4KB None
0b01100 8KB Register bit [12] must be zero
0b01101 16KB Register bits [13:12] must be zero
0b01110 32KB Register bits [14:12] must be zero
0b01111 64KB Register bits [15:12] must be zero
0b10000 128KB Register bits [16:12] must be zero
0b10001 256KB Register bits [17:12] must be zero
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-47