ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VCVT.F32.F16 , Encoded as op = 0
VCVT.F16.F32 , Encoded as op = 1
where:
Instruction Details
Specifies which half of the operand register or destination register is used for the
operand or destination. If is B, then the T bit is encoded as 0 and the bottom half (bits
[15:0]) of or is used. If is T, then the T bit is encoded as 1 and the top half (bits
[31:16]) of or is used
See Standard assembler syntax fields on page A8-7.
The destination register.
The operand register.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
if half_to_single then
S[d] = FPHalfToSingle(S[m], TRUE);
else
S[d] = FPSingleToHalf(S[m], TRUE);
Exceptions
Undefined Instruction.
Floating-point exceptions: Invalid Operation, Input Denormal, Overflow, Underflow, and Inexact.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-589