Demand test descriptions and error codes - Avaya Support

Table 346: TDM Bus Clock Circuit Status Inquiry Test (#148) 2 of 3
Error
Code
4
8
16
32
Test
Result
Description / Recommendation
FAIL The local oscillator on the Tone-Clock circuit failed.
TDM Bus Clock Circuit Status Inquiry Test (#148)
FAIL The circuitry which detects synchronization timing errors on the
Processor/Tone-Clock circuit has failed.
1. Errors 2, 4, 8, 16, and 32 indicate that there is poor
synchronization between port networks and external facilities. It
may be noticeable to the customer in the form of errors in data
communications. The Tone-Clock circuit is defective. See
Replacing the IPSI or Tone-Clock Circuit Pack.
64 FAIL There has been a loss of valid synchronization timing information
coming into this port network. It has been reported as TDM-CLK Error
Log entries with one or more of Error Types 1025, 1281, 1537, 2049
and 2305.
1. Resolve the errors indicated for TDM-CLK (TDM Bus Clock). No
separate corrective action is required.
65 FAIL The Processor/Tone-clock is currently not able to lock on to the current
synchronization reference. If this tone-clock is in the master port
networK:
1. Examine the error log for any DS1-BD, SYNC or other TDM-CLK
errors and resolve as applicable.
2. Run this test again using test tone-clock location.
3. Examine the DS1 measurements to determine whether the facility
is healthy.
4. Administer a new synchronization reference.
5. Replace the DS1 board currently supplying the reference.
If this tone-clock is in the slave port network:
6. Examine the error log for any SYNC, EXP-INTF, or TDM-CLK
errors.
7. Run this test again with test tone-clock location.
2 of 3
Issue 5 May 2009 1259