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Demand test descriptions and error codes - Avaya Support

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Notes to Facility Fault Sectionalization Flowchart<br />

1. Loop transmit to receive on the system side.<br />

Remove the transmit signal from the TN722, TN767, or TN464 circuit pack inputs <strong>and</strong><br />

outputs <strong>and</strong> loop it around to the receive signal going toward the TN722, TN767, or TN464<br />

circuit pack at the first unit wired to the TN722, TN767, or TN464 circuit pack.<br />

The looparound signal may take different forms depending on the installation.<br />

● In some cases, the unit connected to the system may provide a switch or a terminal<br />

interface to control the desired looparound. Make sure that the signal is looped toward<br />

the system <strong>and</strong> that the timing signal is looped.<br />

● In most cases, it may be necessary to temporarily rewire connections at the<br />

cross-connect fields to loop the signal back toward the switch.<br />

The point at which the signal is looped should be one at which physical access is easy <strong>and</strong><br />

where the signal level is within the line compensation (i.e. equalization) range of the<br />

hardware connected. A few cases exist where access to the looparound cot be easily<br />

provided at locations where the signal level is within the line compensation range of the<br />

hardware. Use change ds1 location to change the line compensation.<br />

2. Execute <strong>test</strong> board location for the TN722, TN767 or TN464. Look at results of Test<br />

#144, the Slip Alarm Inquiry <strong>test</strong>. When this <strong>test</strong> fails, the <strong>error</strong> code gives the number of<br />

slips detected since the last Slip Inquiry <strong>test</strong> was run. If the <strong>test</strong> fails, run it at least one<br />

more time to ensure that slips have occurred since the looparound was installed.<br />

Timing Loops<br />

A timing loop exists when a system receives timing from another system whose timing<br />

reference is directly or indirectly derived from itself. The system synchronization pler must avoid<br />

creating a timing loop when administering the synchronization references in a system. Timing<br />

loops can lead to loss of digital data between systems that are exchanging data with any system<br />

within the loop. An invalid timing signal will also be generated by any system within the loop,<br />

thus propagating the invalid timing signal to any system(s) using a system within the loop as a<br />

synchronization reference.<br />

A correctly designed network has no loops, <strong>and</strong> each piece of equipment in the network is<br />

supplied by a clock with an equal or lower stratum number. (For example, the inputs to a<br />

Stratum-3 clock should never be from a Stratum-4 device.)<br />

914 Maintenance Alarms for Communication Manager, Media Gateways <strong>and</strong> Servers

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