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Demand test descriptions and error codes - Avaya Support

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TDM-CLK (TDM Bus Clock)<br />

MO Name<br />

in Log<br />

TDM-CLK MAJ<br />

MIN<br />

Alarm Level Initial Comm<strong>and</strong> to Run Full Name of MO<br />

<strong>test</strong> tone-clock location TDM bus Clock<br />

WRN release tone-clock location<br />

Note:<br />

Note: Replacing the Tone-Clock circuit pack or the IPSI requires a special procedure<br />

described in the documentation for TONE-BD (Tone-Clock Circuit Pack). That<br />

section also describes the LED displays for these circuit packs.<br />

The Time Division Multiplex (TDM) Bus Clock resides on the Tone-Clock circuit, providing<br />

clocking signals both for the TDM bus <strong>and</strong> the LAN Bus. The Tone-Clock circuit is a critical<br />

component in the system <strong>and</strong> is necessary to ensure the operation of every port circuit pack in<br />

the system. The TDM buses of every EPNs is synchronized together. The system timing<br />

reference can be derived internally from the Tone-Clock circuit in any PN, or from an external<br />

(off-board) timing reference. Currently, the TDM bus Clock supports synchronizing the TDM bus<br />

with interface rates from Digital Signal 1 (DS1) facilities as primary or primary <strong>and</strong> secondary<br />

references, (S8700 series: <strong>and</strong> from Stratum-3 clock (STRAT-3) facilities. Only the TN780<br />

tone-clock supports a Stratum-3 clock.)<br />

Moreover, the TN2314 Processor/Tone-Clock circuit pack aids in monitoring <strong>and</strong> selecting<br />

synchronization references. The TN2314 Processor/Tone-Clock circuit pack, after detecting that<br />

the external source of timing is not valid, will automatically begin its escalation procedure,<br />

according to the facilities administered. In the following table, successive losses of signal cause<br />

escalation from left to right.<br />

Switching back to a DS1 source is h<strong>and</strong>led by synchronization maintenance, once any problems<br />

with it are corrected <strong>and</strong> <strong>test</strong>ed.<br />

S8700 series: However, once synchronization has been switched to the internal timing source of<br />

the master Tone-Clock circuit, switching back to a Stratum-3 clock must be initiated by a<br />

technician after the external reference has been repaired.<br />

Table 259: Synchronization - Tone Clock Roles 1 of 2<br />

Tone-Clock<br />

Role<br />

S8700-series<br />

Fiber-PNC<br />

MASTER<br />

Synchronization<br />

Facilities<br />

Initial External<br />

Synchronization<br />

Source<br />

Backup External<br />

Synchronization<br />

Source<br />

964 Maintenance Alarms for Communication Manager, Media Gateways <strong>and</strong> Servers<br />

Internal Source<br />

Stratum-3 clock Source “A” Source “B” Local<br />

oscillator<br />

1 of 2

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