Demand test descriptions and error codes - Avaya Support

SYNC (Port Network Synchronization)
b. Error Type 18: Synchronization Maintenance has been disabled using disable
synchronization-switch. Execute enable synchronization-switch to enable
Synchronization Maintenance reference switching and to resolve this alarm.
c. Error Type 257: problem with the secondary DS1 reference. It is cleared when the
secondary reference is restored. Refer to note (a) to resolve this error substituting
secondary for primary in the preceding resolution steps.
d. Error Type 513: the Tone-Clock circuit pack is providing the timing source for the system.
The primary and secondary (if administered) are not providing a valid timing signal.
Investigate errors 1 and 257 to resolve this error.
e. Error Type 769: excessive switching of system synchronization references has occurred.
When this error occurs, synchronization is disabled and the Tone-Clock circuit pack (in the
master port network) becomes the synchronization reference for the system. Execute the
following steps to resolve this error:
1. Check for timing loops and resolve any loops that exist.
2. Test the active Tone-Clock circuit pack in the master port network using test tone/
clock location long. Check the Error Log for TDM-CLK errors and verify that
TDM Bus Clock Test #148 passes successfully. If Test #148 fails with an Error Code 2
through 32, refer to the TDM-CLK (TDM Bus Clock) Maintenance documentation to
resolve the problem. If not, continue with the following steps.
3. Replace the primary and secondary (if administered) DS1 Interface circuit packs.
4. Check for an error logged against the primary or secondary DS1 board. If there is an
error, follow the DS1 section to resolve the errors. If there is not, enter enable sync,
and wait for two to five minutes for the primary sync source to come on-line.
f. Error Type 2049: the slave Tone-Clock circuit pack is experiencing loss of signal. Refer to
note (i) for error resolution steps.
The following steps should be executed to resolve error 2049 and 2305:
1. Check for timing loops, and resolve any loops that exist.
2. Error 2049:
● Test the Tone-Clock circuit packs in the master and slave port networks using
test tone/clock location long. Check the Error Log for TDM-CLK errors
and verify that TDM Bus Clock Test #148 passes successfully. If Test #148 fails
with an Error Code 2 through 32, refer to TDM-CLK (TDM Bus Clock) to resolve
the problem. If not, continue with the following steps.
● If the system synchronization reference is a Tone-Clock circuit pack and the
master Tone-Clock circuit pack fails TDM Bus Clock Test #150, follow the steps
listed in TDM-CLK (TDM Bus Clock) to replace the master Tone-Clock circuit pack.
Issue 5 May 2009 923